Flexibilis Redundant Switch (FRS)
The Flexibilis Redundant Switch (FRS) is a triple-speed (10Mbps/100Mbps/1Gbps) Ethernet Layer-2 switch that supports new protocols, providing seamless redundancy for Ethernet networking. FRS is compatible with IEC 62439-3 Clause 5 ”High-availability Seamless Redundancy (HSR)” and IEC 62439-3 Clause 4 ”Parallel Redundancy Protocol (PRP)”. The Flexibilis Redundant Switch also includes IEEE1588v2 Precision Time Protocol (PTP) transparent clock functionality. FRS is designed for use in programmable hardware environments (FPGA).
With its 1Gb speed and from 3 to 8 ports it is the highest performing HSR/PRP switch in the market. With FRS no separate RedBox is needed as devices can be connected straight to the FRS, making it a cost-effective solution. Easy licensing method and free evaluation version are all available, as well as a very useful “Getting Started with FRS” training package. The training will help you to choose the correct functionalities for your needs. See also who already uses FRS.
Please read more about how to benefit and take advantage with FRS.
Technical details and features
The Flexibilis Redundant Switch is an FPGA implementation (IP core) of High-availability Seamless Redundancy (HSR) and the Parallel Redundancy Protocol (PRP) integrated into an Ethernet Layer-2 switch. All the ports are triple-speed (10Mbps/100Mbps/1Gbps) and the internal wire-speed forwarding capability (gigabit Full-Duplex at all the ports at the same time) makes it one of the best performing HSR/PRP switches in the market.
Any port can be set to any one of the three speed settings independent of the other ports, so FRS can be used in both gigabit and 100Mbps rings. When FRS is used as a RedBox, it can connect nodes and networks operating at different link speeds than ring to ring.
The HSR protocol is typically used in applications where time synchronization is also needed. Therefore PTP support is an integral part of the FRS IP core. The Flexibilis Redundant Switch includes a transparent end-to-end clock between the ring ports. Having a peer-to-peer transparent clock is also possible, but requires control software (for example the XR7 PTP) running on an attached CPU. When using Gigabit fiber Ethernet, FRS is able to achieve nanosecond class accuracy in clock transfer.
Flexibilis Redundant Switch standard features include:
- Triple-speed (10Mbps/100Mbps/1Gbps), full-duplex operation on all ports
- Compatible with IEC 62439-3 Clause 5 “High-availability Seamless Redundancy (HSR)”
- Compatible with IEC 62439-3 Clause 4 ”Parallel Redundancy Protocol (PRP)”
- Time and frequency synchronization using IEEE1588-2008 Precision Time Protocol v2
- Ethernet packet forwarding at wire-speed, non-blocking
- All of the ports of FRS can be either copper or fiber Ethernet interfaces, or connected to other FPGA blocks
- Ethernet packet filter and prioritization on each of the ports
- Cut-through and Store-and-Forward operation
- HSR RedBox, HSR End-node, HSR QuadBox, PRP RedBox and DANP support
- IEEE1588v2 End-to-end one-step Transparent Clock Functionality
- IEEE1588v2 Peer-to-peer Transparent Clock support functions
- Compatible with IEEE standard 802.1D Media Access Control (MAC) Bridges
- Interface options – MII and GMII (RMII, RGMII, SGMII and 1000BASE-X with separate adapters)
- Register interface for accessing control and status registers
XR7 Redundancy Supervision can be used together with FRS.
For commonly asked questions, please see the Questions & Answers page.
The Flexibilis Redundant Switch is available in several different configurations, from 3-port to 8-port.
For example, a 4-port FRS can be used to implement End-nodes and RedBoxes. Typically one of the Ethernet interfaces is internal, for the device internal CPU to be able to access the network. Two external Ethernet interfaces connect to the HSR ring and the fourth interface is an interlink port. At least a 4-port FRS is recommended, as then no separate RedBoxes are needed and the devices can be connected straight to the FRS.
Included in FRS
When you license FRS, you will get the following:
The IP Core in encrypted VHDL format. The evaluation license can be downloaded by filling in the download form here: FRS IP Core Download
Evaluation and licensing
For information on evaluating and licensing FRS, please contact us .
- FES Manual (pdf), FRS included
- FES Reference Design for Altera Cyclone IV and V (zip)
- FES Reference Design for Altera Cyclone V SoC (zip)
- FRS Reference Design Specification (pdf)
- Instructions to an evaluation setup, Cyclone V GT (pdf)
- Instructions to an evaluation setup, Cyclone V GX (pdf)
- Instructions to an evaluation setup, Cyclone IV (pdf)
- Instructions to an evaluation setup, Terasic SoC (pdf)
- Flexibilis Real Time Clock, FRTC (zip)
- HSR & PRP & PTP Test Plan